1. Field of the Invention
The present invention generally relates to chip-to-chip communication and, more particularly, to high speed complementary metal oxide semiconductor (CMOS) pass gate receivers.
2. Description of the Prior Art
When chip-to-chip communication becomes faster and faster, receiver delay becomes a significant portion of the delay budget. There are basically two inverting stages in the receiver. The main function of the inverting stages is to receive the signals, and magnify and send them to internal circuits. However, since chip-to-chip timing is critical in a 400 Mhz system, these two inverting stages produce a significant delay which it is desired to avoid.
A typical receiver is a NAND-INVERTER, as shown in FIG. 1. This receiver has two inputs, one for data input and the other for inhibit input. The data input 11 is connected to the gates of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) 12 and 13. Similarly, the inhibit input 14 connected to the gates of FETs 15 and 16. The FETs 12 and 15 are connected in parallel, while the FETs 13 and 16 are connected in series, forming a NAND gate of conventional design. The output of the NAND gate is connected to the gates of CMOS FETs 17 and 18 connected as a conventional inverter, the output 19 of which is the output of the receiver.
The operation of the receiver is defined by the following truth table:
______________________________________ RI IN ROUT ______________________________________ 1 0 0 ==&gt; functional mode 1 1 1 ==&gt; functional mode 0 0 0 ==&gt; test mode 0 1 0 ==&gt; test mode ______________________________________
As can be seen from the truth table, in functional mode, when the signal RI is a logic "1" it allows the receiver to freely pass a logic "1" or a logic "0". In the test mode, the signal assumes the logic "0" state, forcing the output of the receiver to be a logic "0" for all inputs.
There are two stages of delay; the inverting NAND stage and the inverting inverter stage. In other words, with this receiver design, data has to go through two inverting stages before reaching the internal latch.